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Searched refs:_offset (Results 1 – 25 of 93) sorted by relevance

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/linux-5.15/drivers/thermal/qcom/
A Dtsens.h83 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ argument
84 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
85 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
86 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
87 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
88 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
89 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
90 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
91 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
92 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
[all …]
/linux-5.15/drivers/clk/bcm/
A Dclk-kona.h99 #define POLICY(_offset, _bit) \ argument
101 .offset = (_offset), \
159 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
161 .offset = (_offset), \
171 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
173 .offset = (_offset), \
182 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
184 .offset = (_offset), \
193 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
195 .offset = (_offset), \
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/linux-5.15/drivers/net/ethernet/mellanox/mlxsw/
A Dcore_acl_flex_keys.h52 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
57 .offset = _offset, \
64 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
66 _element, _offset, _shift, _size)
68 #define MLXSW_AFK_ELEMENT_INFO_BUF(_element, _offset, _size) \ argument
70 _element, _offset, 0, _size)
84 #define MLXSW_AFK_ELEMENT_INST(_type, _element, _offset, \ argument
90 .offset = _offset, \
99 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
101 _element, _offset, _shift, _size, 0, false)
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A Ditem.h266 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
268 .offset = _offset, \
282 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
285 .offset = _offset, \
307 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
309 .offset = _offset, \
323 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
326 .offset = _offset, \
348 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
350 .offset = _offset, \
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A Dspectrum_acl.c527 #define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \ argument
530 .offset = _offset, \
536 #define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \ argument
538 _offset, _mask, _shift, _field)
540 #define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \ argument
542 _offset, _mask, _shift, _field)
544 #define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \ argument
545 MLXSW_SP_ACL_MANGLE_ACTION(FLOW_ACT_MANGLE_HDR_TYPE_TCP, _offset, _mask, _shift, _field)
547 #define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \ argument
548 MLXSW_SP_ACL_MANGLE_ACTION(FLOW_ACT_MANGLE_HDR_TYPE_UDP, _offset, _mask, _shift, _field)
/linux-5.15/drivers/clk/tegra/
A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
134 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
141 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
146 #define MUX8(_name, _parents, _offset, \ argument
148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
154 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
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A Dclk-tegra-audio.c52 #define AUDIO(_name, _offset) \ argument
56 .offset = _offset,\
71 #define AUDIO2X(_name, _num, _offset) \ argument
79 .div_offset = _offset,\
/linux-5.15/drivers/pinctrl/mediatek/
A Dpinctrl-mtk-common.h109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
112 .offset = _offset, \
134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
137 .offset = _offset, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
162 .offset = _offset, \
/linux-5.15/drivers/clk/sunxi-ng/
A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
21 .offset = _offset, \
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
/linux-5.15/drivers/bcma/
H A Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
186 bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
189 bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
190 sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
194 SPEX(_field[0], _offset + 0, _mask, _shift); \
195 SPEX(_field[1], _offset + 2, _mask, _shift); \
196 SPEX(_field[2], _offset + 4, _mask, _shift); \
197 SPEX(_field[3], _offset + 6, _mask, _shift); \
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/linux-5.15/drivers/clk/renesas/
A Drcar-gen3-cpg.h35 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
36 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
55 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
56 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
A Drenesas-cpg-mssr.h53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
A Dr8a779a0-cpg-mssr.c83 #define DEF_PLL(_name, _id, _offset) \ argument
85 .offset = _offset)
87 #define DEF_SD(_name, _id, _parent, _offset) \ argument
88 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
/linux-5.15/tools/objtool/include/objtool/
A Delf.h105 #define for_offset_range(_offset, _start, _end) \ argument
106 for (_offset = ((_start) & OFFSET_STRIDE_MASK); \
107 _offset >= ((_start) & OFFSET_STRIDE_MASK) && \
108 _offset <= ((_end) & OFFSET_STRIDE_MASK); \
109 _offset += OFFSET_STRIDE)
/linux-5.15/drivers/video/fbdev/vermilion/
A Dvermilion.h240 #define VML_READ32(_par, _offset) \ argument
241 (ioread32((_par)->vdc_mem + (_offset)))
242 #define VML_WRITE32(_par, _offset, _value) \ argument
243 iowrite32(_value, (_par)->vdc_mem + (_offset))
/linux-5.15/net/rxrpc/
A Dinsecure.c21 size_t *_buf_size, size_t *_data_size, size_t *_offset) in none_how_much_data() argument
24 *_offset = 0; in none_how_much_data()
46 unsigned int *_offset, unsigned int *_len) in none_locate_data() argument
A Drecvmsg.c318 unsigned int *_offset, unsigned int *_len, in rxrpc_locate_data() argument
344 *_offset = offset; in rxrpc_locate_data()
347 call->security->locate_data(call, skb, _offset, _len); in rxrpc_locate_data()
358 size_t len, int flags, size_t *_offset) in rxrpc_recvmsg_data() argument
428 remain = len - *_offset; in rxrpc_recvmsg_data()
443 *_offset += copy; in rxrpc_recvmsg_data()
449 ASSERTCMP(*_offset, ==, len); in rxrpc_recvmsg_data()
/linux-5.15/tools/testing/selftests/powerpc/nx-gzip/include/
A Dnxu.h428 #define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \
430 #define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \
438 << (31-REG##_offset)))
442 << (31-REG##_offset)))
453 & REG##_mask) << (31-REG##_offset))))
455 | (((X) & REG##_mask) << (31-REG##_offset))))
/linux-5.15/drivers/pinctrl/berlin/
A Dberlin.h37 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
40 .offset = _offset, \
/linux-5.15/drivers/ssb/
H A Dpci.c171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
172 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
174 out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
175 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
177 SPEX16(_outvar, _offset, _mask, _shift)
179 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
181 SPEX(_field[0], _offset + 0, _mask, _shift); \
182 SPEX(_field[1], _offset + 2, _mask, _shift); \
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/linux-5.15/drivers/clk/st/
A Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
39 .offset = _offset, \
/linux-5.15/arch/powerpc/boot/
H A Dlibfdt-wrapper.c33 unsigned long _offset = (off); \
34 check_err(_offset) ? NULL : (void *)(_offset+1); \
/linux-5.15/drivers/net/wireless/realtek/rtlwifi/
A Defuse.h74 void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
79 void read_efuse(struct ieee80211_hw *hw, u16 _offset,
/linux-5.15/drivers/staging/r8188eu/core/
A Drtw_efuse.c147 u16 _offset, in ReadEFuseByte() argument
156 Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf); in ReadEFuseByte()
161 rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff)); in ReadEFuseByte()
163 rtw_write8(Adapter, EFUSE_CTRL + 2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc)); in ReadEFuseByte()
205 static void efuse_ReadEFuse(struct adapter *Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 … in efuse_ReadEFuse() argument
207 Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, pseudo); in efuse_ReadEFuse()
/linux-5.15/drivers/clk/
A Dclk-stm32mp1.c1155 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1162 .reg_off = _offset,\
1182 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1190 .reg_off = _offset,\
1199 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument
1200 DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1203 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1211 .reg_off = _offset,\
1286 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1288 _GATE_MP1(_offset, _bit_idx, _gate_flags))
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