| /linux-5.15/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | link_enc_cfg.h | 40 struct dc_state *state);
54 struct dc_state *state,
65 struct dc_state *state,
73 struct dc_state *state,
78 struct dc_state *state,
83 struct dc_state *state,
89 const struct dc_state *state);
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| A D | hw_sequencer.h | 41 struct dc_state;
63 struct dc_state *context);
65 struct dc_state *context);
69 int num_planes, struct dc_state *context);
71 struct dc_state *context);
73 struct dc_state *context);
75 struct dc_state *context);
95 struct dc_state *context, bool lock);
139 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);
140 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);
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| A D | core_types.h | 78 struct dc_state *state,
89 struct dc_state;
106 struct dc_state *context,
109 struct dc *dc, struct dc_state *context,
114 struct dc *dc, struct dc_state *context);
117 struct dc_state *context,
129 struct dc_state *state,
139 struct dc_state *state,
144 struct dc_state *context);
147 struct dc_state *context,
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| A D | resource.h | 89 struct dc_state *context,
96 struct dc_state *context);
139 struct dc_state *context,
150 const struct dc_state *old_context,
151 struct dc_state *context,
155 const struct dc_state *src_ctx,
156 struct dc_state *dst_ctx);
160 struct dc_state *context,
165 struct dc_state *context,
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| A D | hw_sequencer_private.h | 53 struct dc_state;
74 void (*init_pipes)(struct dc *dc, struct dc_state *context);
75 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
99 struct dc_state *context,
124 void (*update_odm)(struct dc *dc, struct dc_state *context,
128 struct dc_state *context);
134 struct dc_state *context);
141 void (*PLAT_58856_wa)(struct dc_state *context,
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.h | 54 struct dc_state *context,
58 struct dc_state *state,
118 struct dc_state *context,
121 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
124 struct dc_state *context);
127 struct dc_state *context,
134 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
155 struct dc_state *context,
162 struct dc *dc, struct dc_state *context,
167 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc…
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| A D | dcn20_hwseq.h | 37 struct dc_state *context);
40 struct dc_state *context);
66 struct dc_state *context);
69 struct dc_state *context);
72 struct dc_state *context);
75 struct dc_state *context);
78 struct dc_state *context,
107 struct dc_state *context);
111 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer.h | 45 struct dc_state *context,
49 struct dc_state *context);
52 struct dc_state *context);
77 struct dc_state *context);
81 struct dc_state *context,
85 struct dc_state *context);
103 struct dc_state *context);
106 void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
110 struct dc_state *context);
115 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_resource.h | 47 struct dc_state *context,
56 bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
59 struct dc *dc, struct dc_state *context,
63 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
68 struct dc *dc, struct dc_state *context,
87 struct dc_state *new_ctx,
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| A D | dcn30_hwseq.h | 37 struct dc_state *context);
41 struct dc_state *context);
45 struct dc_state *context);
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.h | 30 struct dc_state *context,
34 struct dc_state *context,
37 struct dc_state *context, bool safe_to_lower);
49 struct dc_state *context,
54 struct dc_state *context);
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_hw_sequencer.h | 33 struct dc_state;
40 struct dc_state *context);
58 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
68 struct dc_state *context);
72 struct dc_state *context);
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/dce112/ |
| A D | dce112_resource.h | 42 struct dc_state *context,
43 struct dc_state *old_context);
47 struct dc_state *context,
52 struct dc_state *new_ctx,
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_link_enc_cfg.c | 65 struct dc_state *state, in update_link_enc_assignment()
116 const struct dc_state *state) in find_first_avail_link_enc()
132 struct dc_state *state, in get_stream_using_link_enc()
158 struct dc_state *state) in link_enc_cfg_init()
172 struct dc_state *state, in link_enc_cfg_link_encs_assign()
217 struct dc_state *state, in link_enc_cfg_link_enc_unassign()
233 struct dc_state *state, in link_enc_cfg_is_transmitter_mappable()
247 struct dc_state *state, in link_enc_cfg_get_link_using_link_enc()
272 struct dc_state *state, in link_enc_cfg_get_link_enc_used_by_link()
305 const struct dc_state *state) in link_enc_cfg_get_next_avail_link_enc()
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| A D | dc.c | 170 static int get_seamless_boot_stream_count(struct dc_state *ctx) in get_seamless_boot_stream_count()
928 struct dc_state *context) in disable_all_writeback_pipes_for_stream()
936 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, in apply_ctx_interdependent_lock()
959 static void disable_dangling_plane(struct dc *dc, struct dc_state *context) in disable_dangling_plane()
962 struct dc_state *dangling_context = dc_create_state(dc); in disable_dangling_plane()
963 struct dc_state *current_ctx; in disable_dangling_plane()
1007 struct dc_state *context) in disable_vbios_mode_if_required()
1063 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context) in wait_for_no_pipes_pending()
1197 struct dc_state *ctx) in enable_timing_multisync()
1221 struct dc_state *ctx) in program_timing_sync()
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_hwseq.h | 41 struct dc_state *context);
45 struct dc_state *context);
47 void dcn21_PLAT_58856_wa(struct dc_state *context,
56 struct dc_state *context, struct dc_stream_state *stream);
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| A D | dcn21_hwseq.c | 100 struct dc_state *context) in dcn21_exit_optimized_pwr_state()
110 struct dc_state *context) in dcn21_optimize_pwr_state()
129 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) in dcn21_PLAT_58856_wa()
233 struct dc_state *context, struct dc_stream_state *stream) in dcn21_is_abm_supported()
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_stream.h | 308 struct dc_state *state);
342 struct dc_state *new_ctx,
347 struct dc_state *new_ctx,
355 struct dc_state *context);
361 struct dc_state *context);
366 struct dc_state *context);
373 struct dc_state *context);
384 struct dc_state *state,
413 struct dc_state *context,
418 void dc_trigger_sync(struct dc *dc, struct dc_state *context);
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| A D | dc.h | 281 struct dc_state;
515 struct dc_state;
648 struct dc_state *current_state;
1050 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1061 struct dc_state *new_ctx,
1067 struct dc_state *dst_ctx);
1078 const struct dc_state *src_ctx,
1079 struct dc_state *dst_ctx);
1083 struct dc_state *dst_ctx);
1085 void dc_resource_state_destruct(struct dc_state *context);
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| A D | dce110_clk_mgr.h | 34 const struct dc_state *context,
40 struct dc_state *context);
42 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/dce100/ |
| A D | dce100_hw_sequencer.h | 33 struct dc_state;
39 struct dc_state *context);
43 struct dc_state *context);
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_hwseq.h | 53 struct dc_state *context);
55 struct dc_state *context, struct dc_stream_state *stream);
56 void dcn31_init_pipes(struct dc *dc, struct dc_state *context);
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| /linux-5.15/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_mst_types.c | 747 struct dc_state *dc_state, in compute_mst_dsc_configs_for_link() argument
761 for (i = 0; i < dc_state->stream_count; i++) { in compute_mst_dsc_configs_for_link()
764 stream = dc_state->streams[i]; in compute_mst_dsc_configs_for_link()
851 struct dc_state *dc_state, in compute_mst_dsc_configs_for_state() argument
859 for (i = 0; i < dc_state->stream_count; i++) in compute_mst_dsc_configs_for_state()
862 for (i = 0; i < dc_state->stream_count; i++) { in compute_mst_dsc_configs_for_state()
863 stream = dc_state->streams[i]; in compute_mst_dsc_configs_for_state()
879 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) in compute_mst_dsc_configs_for_state()
883 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars)) { in compute_mst_dsc_configs_for_state()
889 for (j = 0; j < dc_state->stream_count; j++) { in compute_mst_dsc_configs_for_state()
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| A D | amdgpu_dm_mst_types.h | 51 struct dc_state *dc_state,
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| /linux-5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| A D | dce_clk_mgr.h | 37 struct dc_state *context);
39 uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context);
|