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Searched refs:smnPCIE_LC_LINK_WIDTH_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-5.15/drivers/gpu/drm/amd/amdgpu/ !
A Dnbio_v2_3.c54 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
483 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_lc_spc_mode_wa()
506 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_l1_link_width_reconfig_wa()
508 WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data); in nbio_v2_3_apply_l1_link_width_reconfig_wa()
/linux-5.15/drivers/gpu/drm/amd/pm/swsmu/smu13/ !
A Dsmu_v13_0.c68 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
1873 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v13_0_get_current_pcie_link_width_level()
/linux-5.15/drivers/gpu/drm/amd/pm/swsmu/smu11/ !
A Dsmu_v11_0.c72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
2115 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v11_0_get_current_pcie_link_width_level()
/linux-5.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ !
A Dvega12_hwmgr.c51 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
2205 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega12_get_current_pcie_link_width_level()
A Dvega20_hwmgr.c56 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
3314 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_get_current_pcie_link_width_level()
A Dvega10_hwmgr.c58 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
4612 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega10_get_current_pcie_link_width_level()